For Data organization and architecture homework: Please explain if possible question 1 through 8. I really appreciate the explanationsHomework 7 Assume that the logic blocks needed to implement a processors datapath have the followinglatencies: 200p§ 70m 20p§ 90p§ 909s 250p§ 15gb; lORs 1. If the only thing we need to do in a processor is fetch consecutive instructions, whatwould the cycle time be? 2. Consider a processor that only has one type of instruction: unconditional branch. Whatwould the cycle time for this datapath? 3. Consider a processor that only has one type of instruction: conditional branch. Whatwould the cycle time for this datapath? The coming three questions refer to the datapath element Shift-left-Z: 4. Which kinds of instructions require this resource?5. For which kinds if instructions is this resource on the path? Assume the following latencies for logic blocks in the databath: Immm-mmmmwmmm 6. What is the clock cycle time if the only type of instructions we need to support are ALUinstructions (add, and, etc.) 7. What is the clock cycle time if we only hayejtg support (by) instructions?8. What is the clock cycle time if we must support (add, peg, lyy, and s35) instructions?
Data organization and architecture
Plagiarism-free and delivered on time!
We are passionate about delivering quality essays.
Our writers know how to write on any topic and subject area while meeting all of your specific requirements.
Unlike most other services, we will do a free revision if you need us to make corrections even after delivery.
How it Works
Place an order
Fill out the order form.
Attach any custom instructions that is required to complete your order.
Pay online safely.
The order form will redirect you to a payment page.
Receive Order via Email
Once the order is complete, we’ll send it via the email provided on the order form.